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| description the CXD2412AQ is a timing signal generator for lcd panel drivers. features generates the lcx007 drive pulse. supports ntsc/pal. (with pal, a video signal on which scanning line conversion has been performed is used.) supports wide. supports hd (20 mhz band). supports muse-ntsc conversion signal (mndc). supports up/down and/or right/left inversion. supports three-panel projector. generates timing signal of external sample-and- hold circuit. generates line inversion and field inversion signals. ac drive for lcd panel during no signal. afc circuit supporting static and dynamic fluctuations. applications lcd projectors structure silicon gate cmos ic absolute maximum ratings (ta = 25 ?) supply voltage v dd v ss ?.5 to +7.0 v input voltage v i v ss ?0.5 to v dd + 0.5 v output voltage v o v ss ?0.5 to v dd + 0.5 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? recommended operating conditions supply voltage v dd 5.0 0.5 v operating temperature topr ?0 to +75 ? ?1 CXD2412AQ e94y04-st timing generator for lcd panels sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 100 pin qfp (plastic)
?2 CXD2412AQ block diagram phase comparator h-sync detector h-skew detector v-sync seperater (noise shape) v-timing pulse generator field & line controller pll-counter loop filter half-h killer h-timing pulse generator 2 3 4 5 6 9 10 11 12 13 14 15 16 17 24 25 26 27 28 29 30 40 35 31 46 49 50 53 54 70 65 73 81 82 83 78 88 87 86 79 89 90 98 97 94 91 92 93 1 rpd1 rpd2 rpd3 fpd1 tc1 vst vp2 vp1 xclr tst6 vsync cko1 hsync n.c. n.c. cki1 fpd2 fpd3 tc2 tc3 cki2 cki3 cko2 cko3 tst1 tst2 tst3 tst4 tst5 slaux v ss 0 v ss 1 v ss 2 v ss 3 v ss 4 v ss 5 v ss 6 v ss 7 v ss 8 v ss 10 v ss 11 v ss 12 v dd 0 v dd 1 v dd 2 v dd 3 v dd 4 v dd 5 slsh3 7 8 18 19 20 21 22 23 39 38 37 36 34 32 33 41 42 43 44 45 47 48 51 52 55 56 57 58 59 60 69 68 67 63 64 66 61 62 71 72 74 84 75 76 77 85 80 10 0 99 96 95 peo1 peo2 peo3 pwm1 pwm2 pwm3 n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. n.c. slfr frp rgt dwn xrgt hp1 hp6 hp2 hp3 hp4 hp5 pcgw slsh1 slsh2 cp1 cp2 hck1a hck2a hck2b hck1b hsta hstb clr enb vck pcg xclp1 xclp2 prg sh1 sh2 sh3 sh4 ntpl xwd xhd ?3 CXD2412AQ pin description pin no. symbol i/o input pin for open status description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 n.c. n.c. v dd 0 v ss 0 tc1 fpd1 peo1 pwm1 rpd1 v ss 1 cko1 cki1 v ss 2 tst6 v ss 3 hsync vsync hp1 hp2 hp3 hp4 hp5 hp6 tst1 tst2 tst3 tst4 v dd 1 v ss 4 tst5 xclr rgt xrgt hsta v dd 2 hck1a hck2a i o o i o o i i i i i i i i i i i i i i i i i o o o o not connected not connected power supply gnd fpd1 pin pulse width adjustment phase comparator output b-1 (for ntsc/pal) loop filter integrator output 1 loop filter integrator input 1 phase comparator output a-1 (for ntsc/pal) gnd ntsc/pal oscillation cell output ntsc/pal oscillation cell input gnd test gnd hsync input (negative polarity) vsync input (negative polarity) switches for the horizontal display start position switches for the horizontal display start position switches for the horizontal display start position switches for the horizontal display start position switches for the horizontal display start position switches for the horizontal display start position test test test test power supply gnd test cleared at 0 v right/left inversion identification signal input right/left inversion identification signal output h start pulse a power supply h clock pulse 1a h clock pulse 2a l l l l l l h l l l l h h h ?4 CXD2412AQ pin no. symbol i/o input pin for open status description 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 hck1b hck2b v ss 5 hstb clr enb vck pcg vst dwn n.c. vp1 vp2 n.c. n.c. v dd 3 v ss 6 n.c. n.c. n.c. n.c. n.c. n.c. frp xclp1 xclp2 prg v ss 7 sh1 sh2 sh3 sh4 v dd 4 slsh1 slsh2 slaux pcgw o o o o o o o o i i i o o o o o o o o i i i i h clock pulse 1b h clock pulse 2b gnd h start pulse b clear pulse enable pulse v clock pulse precharge pulse v start pulse up/down inversion identification signal input not connected switches for the vertical display start position switches for the vertical display start position not connected not connected power supply gnd not connected not connected not connected not connected not connected not connected ac drive inversion timing output video signal pedestal clamp pulse 1 video signal pedestal clamp pulse 2 precharge signal pulse gnd sample-and-hold pulse 1 sample-and-hold pulse 2 sample-and-hold pulse 3 resample-and-hold pulse power supply switches sh switches sh switches free-running identification line number switches pcg h l h l l h h ?5 CXD2412AQ pin no. symbol i/o input pin for open status description 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 slfr ntpl xwd v dd 5 v ss 8 xhd slsh3 tc2 fpd2 peo2 pwm2 rpd2 v ss 10 cko2 cki2 v ss 11 cko3 cki3 v ss 12 rpd3 peo3 pwm3 fpd3 tc3 cp1 cp2 i i i i i i o o i o o i o i o o i o i i i switches between h inversion and f inversion (h: h inversion / l: f inversion) switches mode switches mode power supply gnd switches mode switches sh fpd2 pin pulse width adjustment phase comparator output b-2 (for wide) loop filter integrator output 2 loop filter integrator input 2 phase comparator output a-2 (for wide) gnd wide oscillation cell output wide oscillation cell input gnd hd/mndc oscillation cell output hd/mndc oscillation cell input gnd phase comparator output a-3 (for hd/mndc) loop filter integrator output 3 loop filter integrator input 3 phase comparator output b-3 (for hd/mndc) fpd3 pin pulse width adjustment switches pedestal clamp position switches pedestal clamp position h h h h l h l ?6 CXD2412AQ electrical characteristics 1. dc characteristics (temperature = 25?, vss = 0v) item symbol conditions min. typ. max. unit supply voltage input voltage input voltage input voltage input voltage output voltage output voltage output voltage output voltage output voltage output voltage input leak current input leak current output leak current current consumption clock input cycle cross point time difference cross point time difference output rise delay output fall delay output rise delay output fall delay hck1, sh1 delay time difference hck1, sh1 delay time difference hck2, sh1 delay time difference hck2, sh1 delay time difference hck1 duty hck2 duty ckin hck1a, hck2a hck1b, hck2b hckl, shm hckl, shm other than hck1 and shm other than hck1 and shm hck1a, hck1b, sh1 hck1a, hck1b, sh1 hck2a, hck2b, sh1 hck2a, hck2b, sh1 hck1a, hck1b hck2a, hck1b ? t ? t tpr tpf tpr tpf dt1 dt2 dt1 dt2 th/th + tl th/th + tl cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf cl = 30pf 22 0.05 1 0.1 1 45 45 10 10 20 15 25 15 0.25 5 0.5 5 52 52 ns ns ns ns ns ns ns ns ns ns ns % % v dd v ih v il v ih v il v oh v ol v oh v ol v oh v ol ii l ii h i lz idd ttl input cell ttl input cell cmos input cell cmos input cell i oh = ?ma (hckl, shm) i ol = 8ma (hckl, shm) i oh = ?ma (ckon, ckin) i ol = 3ma (ckon, ckin) i oh = ?ma (other than the above) i ol = 4ma (other than the above) pull-up resistor connected pull-down resistor connected rpdn, fpdn (at high impedance state) hd mode, v dd = 5.0v (at no load) 4.5 2.2 0.7v dd v dd ? 0.8 v dd /2 v dd ? 0.8 ?0 ?0 ?0 ?00 100 75 5.5 0.8 0.3v dd 0.4 v dd /2 0.4 ?40 240 40 v v v v v v v v v v v ? ? ? ma 2. ac characteristics (v dd = 5.0 10%) item applicable pins symbol conditions min. typ. max. unit note) l = 1a, 1b, 2a, 2b n = 1, 2, 3 m = 1, 2, 3, 4 ?7 CXD2412AQ timing definition t pr t pf output output ck1 v dd 0v v dd 0v v dd 0v tt 50% 50% 50% t h t l t 2 t 1 50% 50% dt 1 dt 2 hck1a 1b 2a 2b ck1 sh1 50% 50% 50% 50% d t d t v dd 0v v dd 0v hck1a hck1b (hck2a) (hck2b) ?8 CXD2412AQ lcd panel structure the structure of lcd panels driven by this ic is shown below. dot arrangement (1) (16 : 9 display) the dots are arranged in a delta pattern. the shaded area is used for the dark border around the display. the r corresponds to sig2, g to sig1, and b to sig3, respectively. r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r a a a a a a a a a a a a b b r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r b gate sw dl1 gate sw dl2 gate sw dl3 gate sw dl4 gate sw 1 gate sw 2 gate sw gate sw 44 gate sw 45 gate sw 46 gate sw 47 gate sw 48 gate sw 311 gate sw 312 gate sw 313 gate sw 314 gate sw gate sw 356 gate sw 357 gate sw dr1 gate sw dr2 gate sw dr3 gate sw dr4 side black 4:3 area side black odd = 13 even = 14 odd = 135 even = 134 odd = 1094 even = 1095 odd = 1069 even = 1068 odd = 799 even = 800 odd = 135 even = 134 odd = 13 even = 13 479 480 1 2 3 4 3 480 3 r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b gr g b g br g b g br g b g br g b g br g g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b gr g b g br g b g br g b g br g b g br g g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r b r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r ?9 CXD2412AQ dot arrangement (2) (4 : 3 display) the dots are arranged in a delta pattern. the shaded area is used for the dark border around the display. the r corresponds to sig2, g to sig1, and b to sig3, respectively. b r b g r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r b gate sw dl1 gate sw dl2 gate sw dl3 gate sw dl4 gate sw 1 gate sw 2 gate sw gate sw 44 gate sw 45 gate sw 46 gate sw 47 gate sw 48 gate sw 311 gate sw 312 gate sw 313 gate sw 314 gate sw gate sw 356 gate sw 357 gate sw dr1 gate sw dr2 gate sw dr3 gate sw dr4 side black 4:3 area side black odd = 13 even = 14 odd = 135 even = 134 odd = 1094 even = 1095 odd = 1069 even = 1068 odd = 799 even = 800 odd = 135 even = 134 odd = 13 even = 13 479 480 1 2 3 4 3 480 3 r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b gr g b g br g b g br g b g br g b g br g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b gr g b g br g b g br g b g br g b g b g g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r b r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r r g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b g br g b r r r r r r r r r r r r r r r r r r r r r r ?10 CXD2412AQ input signal specifications 1. horizontal sync signal with ntsc, ntsc wide, pal, pal+, and mndc, the standard signal is doubled in speed, and a 1/2 cycle, 1/2 width horizontal sync signal (h.sync) is input. with hd, a signal derived by cutting off the lower part of 3-value sync is input. negative polarity input is used. 2. vertical sync signal v.sync separated by synchronizing separation circuit and not doubled in speed is input as the vertical sync signal. negative polarity input is used. with this tg, the phase relationship between vsync and hsync is as follows; (1) ntsc/ntsc wide/mndc (2) pal/pal+ (3) hd phase reference hsync vsync (double-speed h.sync) phase reference hsync vsync the video signal has a 487-line effective period due to scanning line conversion. (double-speed h.sync ) hsync vsync phase reference hsync vsync odd field even field ?11 CXD2412AQ mode selection mode selection is performed by means of three pins, as shown in the table. ntpl h l h l l h xwd h h l l x x xhd h h h h l l mode ntsc pal ntsc wide pal+ hd mndc ?12 CXD2412AQ slsh1 = h slsh2 = h slsh3 = l slsh1 = l slsh2 = h slsh3 = l slsh1 = h slsh2 = l slsh3 = l slsh1 = l slsh2 = l slsh3 = l right scan driver rgt = h hck1a (hck1b) sh1 sh2 sh3 sh4 left scan driver rgt = l sh1 sh2 sh3 sh4 hck1a (hck1b) sh pulse switching the phase relationship between hck1a, hck1b and sh1, sh2, sh3, sh4 is switched by slsh1, slsh2, slsh3. ?13 CXD2412AQ slsh1 = h slsh2 = h slsh3 = h slsh1 = l slsh2 = l slsh3 = h right scan driver hck1a (hck1b) sh1 sh2 sh3 sh4 left scan driver sh1 sh2 sh3 sh4 hck1a (hck1b) rgt = h slsh1 = h slsh2 = l slsh3 = h rgt = l slsh1 = l slsh2 = h slsh3 = h ?14 CXD2412AQ right/left inversion and up/down inversion the lcd panel is arranged in a delta pattern, where an identical signal line is 1.5-dot offset for every horizontal line. for this reason, a 1.5-bit offset is made to the horizontal start pulse hst of the lcd between lines. hck and s/h (sample and hold) are also 1.5-bit offset in a similar manner. when the panel is driven with right/left inversion or up/down inversion, this offset relationship becomes inverted for even and odd lines. moreover, since the dot arrangement is asymmetrical, the hst position is also offset. right/left inversion and up/down inversion are supported by the tg as follows. (1) two types of output pulses for right scan (a output) and left scan (b output) are prepared for hst, hck to allow right/left inversion present/absent mixed three-panel lcds to be driven simultaneously. in addition, xrgt (rgt inverse output) is prepared for the left scan panel. sh1 and sh3 connections to the driver are reversed for sample-and-hold. (2) left scan pulses are output to the a output by setting the right/left inversion input pin rgt to low. also, xrgt is driven high by setting rgt to low. (3) the a and b outputs output up scan pulses by setting the up/down inversion input pin dwn to low. h scanner display area v scanner down scan up scan right scan left scan tg sh1 sh2 sh3 sh4 sh1 sh2 sh3 sh4 a output driver sh1 sh2 sh3 sh4 b output driver right/left inversion compatible sh wiring diagram the relationship between the output pins and switches is summarized below. tg input pin a output hst, hck b output hst, hck (three-panel lcd auxiliary output) for right scan, down scan for left scan, down scan for right scan, up scan for left scan, up scan for left scan, down scan for right scan, down scan for left scan, up scan for right scan, up scan dwn h h l l rgt h l h l ?15 CXD2412AQ horizontal output pulses the hst pulses are offset for each line in accordance with the dot arrangement. video start ?.5fh ?.5fh ?fh ?.5fh ?.5fh ?fh mck hstn n = a.b 16 : 9, right, down scan, even line 16 : 9, right, up scan, odd line 16 : 9, left, down scan, even line 16 : 9, left, up scan, odd line 4 : 3, right, down scan, odd line 4 : 3, left, down scan, odd line 4 : 3, right, up scan, even line 4 : 3, left, up scan, even line 4 : 3, right, down scan, even line 4 : 3, right, up scan, odd line 4 : 3, left, down scan, even line 4 : 3, left, up scan, odd line 16 : 9, right, down scan, odd line 16 : 9, left, down scan, odd line 16 : 9, right, up scan, even line 16 : 9, left, up scan, even line ?16 CXD2412AQ the phase relationship between the horizontal pulses is shown in the figure below. the display start position can be changed by means of the hp pin while maintaining this relationship. 1 s 0.7 s 1.2 s 0.4 s 3.1 s 1.2 s 0.55 s 2 s 0.15 s hsync hstn n = a.b vck frp pcg frp prg enb clr xclp1 xclp2 ?17 CXD2412AQ xclp pulse switching the phase relationship between hsync and xclp1, xclp2 is switched by means of cp1 and cp2. ?50ns ?50ns 550ns 150ns 1350ns 950ns 2150ns 1750ns 2550ns cp1 = l; cp2 = l cp1 = h; cp2 = l cp1 = l; cp2 = h cp1 = h; cp2 = h cp1 = l; cp2 = l cp1 = h; cp2 = l cp1 = l; cp2 = h cp1 = h; cp2 = h hsync xclp1 central value xclp2 central value ?18 CXD2412AQ vertical output the vertical display position is varied as shown below. vp1 l h l h vp2 l l h h after 2h after 1h central value 1h before ntsc ntsc-wide mndc pal pal+ hd 545h 641h 577h all modes 769h lcd panel ac driving for no signal with no signal, also, provision is made as follows for ac driving of the lcd panel. horizontal pulses the pll is set to the free-running state. therefore, the horizontal pulse frequency depends on the pll free-running frequency. vertical pulses the number of lines is counted by an internal counter, and vst and frp are output in a specific cycle. vst cycle with no signal slaux = l slaux = h note) this tg determines there to be no signal if there is no vsync input during the above cycle. ?19 CXD2412AQ ntsc-odd line horizontal direction timing chart 885 895 905 915 925 935 945 955 965 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?20 CXD2412AQ ntsc-even line horizontal direction timing chart 885 895 905 915 925 935 945 955 965 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?21 CXD2412AQ pal-odd line horizontal direction timing chart 929 939 949 959 969 979 989 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?22 CXD2412AQ pal-even line horizontal direction timing chart 929 939 949 959 969 979 989 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?23 CXD2412AQ nt-wide-odd line horizontal direction timing chart 1205 1215 1225 1235 1245 1255 1265 1275 1285 1295 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?24 CXD2412AQ nt-wide-even line horizontal direction timing chart 1205 1215 1225 1235 1245 1255 1265 1275 1285 1295 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?25 CXD2412AQ pal+ -odd line horizontal direction timing chart 1235 1245 1255 1265 1275 1285 1295 1305 1315 1325 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?26 CXD2412AQ pal+ -even line horizontal direction timing chart 1235 1245 1255 1265 1275 1285 1295 1305 1315 1325 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?27 CXD2412AQ hd-odd line horizontal direction timing chart 1280 1290 1300 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 1310 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?28 CXD2412AQ hd-even line horizontal direction timing chart 1280 1290 1300 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 1310 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?29 CXD2412AQ mndc-odd line horizontal direction timing chart 1277 1287 1297 1317 1327 1337 1347 1357 1367 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 1307 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?30 CXD2412AQ mndc-even line horizontal direction timing chart 1277 1287 1297 1317 1327 1337 1347 1357 1367 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 1307 mck hsync xclp1 sh1 xclp2 sh2 sh3 sh4 hck1a hck2a hsta hck1b hck2b enb hstb clr vck frp pcg prg note) input pins in default state. ?31 CXD2412AQ ntsc/ntsc wide/mndc vertical direction timing chart hsync vsync blk xclp vst vck frp hst enb vres frp 21h start of display 1st display line 1 2' 3 4' 5 6' 7 8' 1 2 3 4 5 483' 482 (internal pulse) (f inversion) (h inversion) (double-speed sync) ?32 CXD2412AQ pal/pal+ vertical direction timing chart hsync vsync blk xclp vst vck frp hst enb vres frp 20h start of display 1st display line 1 2 3 4 5 6 7 8 1 2 3 4 5 9 10 11 12 13 14 15 16 17 18 19 20 (f inversion) (h inversion) (internal pulse) ?33 CXD2412AQ hd-odd field vertical direction timing chart hsync vsync blk xclp vst vck frp hst enb vres frp 45h start of display 1st display line 1 2 3 4 5 6 7 8 1 2 3 4 5 9 10 11 12 13 14 15 16 17 18 19 20 (h inversion) (f inversion) (internal pulse) 1035 ?34 CXD2412AQ hd-even field vertical direction timing chart hsync vsync blk xclp vst vck frp hst enb vres frp start of display 1st display line 1 2 3 4 5 (h inversion) (f inversion) (internal pulse) 538 533 528 523 518 517 ?35 CXD2412AQ 0.01 +5.0v 47 16v 0.01 +5.0v 47 16v 0.01 47 16v 0.01 47 16v 0.01 47 16v 0.01 47 16v rgt h l xhd h l xwid h l ntpl h l slfr h l pcgw h l slaux h l slsh1 h l slsh2 h l vp2 h l vp1 h l dwn h l hp2 h l 0.01 100p 33 25v 0.01 50k 50k 50k 100p 100p +5.0v 0.01 3.3 1k 33k 33k 0.1 0.5 33 25v 33k 50k 0.01 10k 20p 5.1k 1000p 10k +13.0v 0.01 3.3 1k 33k 33k 0.1 1 33 25v 33k 50k 0.01 10k 0.01 5.1k 1000p 10k +13.0v 0.01 33 25v 33k +13.0v 10k 1k 5.1k 0.1 33k 3.3 0.5 20p 1000p 0.01 50k 10k 20p s1030 top view hp3 12 45 c 10k 10k 10k 10k hp1 h l cp1 h l cp2 h l +5.0v 0.01 33k +5.0v 40 39 38 37 36 35 34 31 32 33 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 70 69 68 67 63 64 65 66 61 62 71 72 73 74 75 76 77 78 79 80 slsh3 tc2 fpd2 peo2 pwm2 rpd2 v ss cko2 cki2 cko3 cki3 rpd3 v ss v ss peo3 pwm3 fpd3 tc3 cp1 cp2 vp2 vp1 n.c. dwn vst pcg vck enb clr v ss hck2b hck2a hstb hck1b hck1a v dd hsta xrgt rgt xclr xhd v ss v dd xwid ntpl slfr pcgw slaux slsh2 v dd sh4 sh2 slsh1 sh3 sh1 v ss prg xclp2 xclp1 frp n.c. n.c. n.c. n.c. n.c. n.c. v ss v dd n.c. n.c. 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 n.c. n.c. v dd v ss tc1 fpd1 peo1 pwm1 rpd1 cko1 cki1 tst6 v ss v ss v ss hsync vsync hp1 hp2 hp3 hp4 hp5 tst1 hp6 tst2 tst3 tst4 v dd v ss tst5 81 82 83 84 88 87 86 85 89 90 10 0 99 98 97 96 94 91 92 93 95 h slsh3 l application circuit application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. ?36 CXD2412AQ package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy package structure 23.9 0.4 qfp-100p-l01 detail a m 100pin qfp (plastic) 20.0 ?0.1 + 0.4 0?to 15 0.15 ?0.05 + 0.1 15.8 0.4 17.9 0.4 14.0 ?0.01 + 0.4 2.75 ?0.15 + 0.35 a 0.65 0.12 0.15 0.8 0.2 (16.3) * qfp100-p-1420-a 1.4g |
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